1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device and a method for driving the semiconductor memory device.
2. Description of the Related Art
In general, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device includes a buffer for transforming an external input signal, e.g., a signal of a Transistor-Transistor Logic (TTL) level, into an internal signal of the semiconductor memory device, e.g., a signal of a CMOS level. The buffer includes a command buffer for buffering an external command and outputting an internal command and an address buffer for buffering an external address and outputting an internal address.
FIG. 1 is a block view illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a plurality of address buffers BUF1 and BUF2 for buffering a plurality of addresses A<18:0> that are inputted from the outside and outputting a plurality of internal addresses PA<18:0>, and a command buffer BUF3 for buffering an external command CMDB and outputting an internal command PCMD. Here, two address buffers BUF1 and BUF2 are illustrated for illustration purposes, but the address buffers BUF1 and BUF2 are provided corresponding to the addresses A<18:0> one-to-one.
Meanwhile, the address buffers BUF1 and BUF2 and the command buffer BUF3 maintain an enabled state in response to an enable signal BUFEN regardless of a read/write operation mode.
Here, the conventional semiconductor memory device having the above-described structure has the following features.
FIG. 2 shows a table describing Burst Ordering Specification according to a read/write operation mode.
Referring to FIG. 2, the 0th, first and second addresses A<0:2> are received and used during a read operation mode to perform a burst ordering control regardless of a burst length. On the other hand, when a burst length is 4 during a write operation mode, the second address A<2> is received and used among the 0th, first and second addresses A<0:2>.
FIG. 3 shows a timing diagram of a conventional semiconductor memory device in a write operation mode.
Referring to FIG. 3, it may be seen that a data is inputted through a data pad DQ after a write command WT is inputted and a CAS Write Latency (CWL) passes. Here, since the enable signal BUFEN maintains the enabled state in a logic high level continuously, all the address buffers BUF1 and BUF2 maintain the enabled state.
Therefore, the conventional semiconductor memory device incurs excessive power consumption because the address buffer BUF1 or BUF2 for receiving a particular address A<0:1> or A<0:2> is enabled all the time, although the conventional semiconductor memory device does not use the particular address A<0:1> or A<0:2> during a write operation mode.